Reducing wafer distortion through a high cte layer

ABSTRACT

Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides. At least one of the first and second sides includes a silicon (111) surface. The method includes forming a high coefficient-of-thermal-expansion (CTE) layer on the first side of the silicon substrate. The high CTE layer has a CTE greater than the CTE of silicon. The method includes forming a buffer layer over the second side of the silicon substrate. The buffer layer has a CTE greater than the CTE of silicon. The method includes forming a III-V family layer over the buffer layer. The III-V family layer has a CTE greater than the CTE of the buffer layer.

PRIORITY DATA

This application is a divisional application of U.S. application Ser.No. 12/956,145, filed Nov. 30, 2010, which is hereby incorporated byreference in its entirety.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapidgrowth in recent years. Technological advances in IC materials anddesign have produced various types of ICs that serve different purposes.The fabrication of some types of ICs may require forming a III-V familylayer on a substrate, for example forming a gallium nitride layer on asubstrate. These types of IC devices may include, as examples,light-emitting diode (LED) devices, radio frequency (RF) devices, andhigh power semiconductor devices.

Traditionally, manufacturers have formed the III-V family layer on asapphire substrate. However, sapphire substrates are expensive. Thus,some manufacturers have been attempting to form III-V layers on asilicon substrate, which is cheaper. However, existing methods offorming a III-V family layer on a silicon substrate may result in waferbending or distortion, especially if the fabrication involves drastictemperature changes. The wafer distortion may lead to wafer defects,which reduces yield and degrades device performance.

Therefore, while existing methods of forming III-V family layers onsilicon substrates have been generally adequate for their intendedpurposes, they have not been entirely satisfactory in every aspect.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isemphasized that, in accordance with the standard practice in theindustry, various features are not drawn to scale. In fact, thedimensions of the various features may be arbitrarily increased orreduced for clarity of discussion.

FIG. 1 is a flowchart illustrating a method for fabricating asemiconductor device according to various aspects of the presentdisclosure.

FIGS. 2-6 are diagrammatic fragmentary cross-sectional side views of aportion of a semiconductor device at various stages of fabrication inaccordance with various aspects of the present disclosure.

FIGS. 7-9 are diagrammatic fragmentary cross-sectional side views of aportion of another semiconductor device at various stages of fabricationin accordance with various aspects of the present disclosure.

FIGS. 10-11 are diagrammatic fragmentary cross-sectional side views of aportion of yet another semiconductor device at various stages offabrication in accordance with various aspects of the presentdisclosure.

DETAILED DESCRIPTION

It is to be understood that the following disclosure provides manydifferent embodiments, or examples, for implementing different featuresof the invention. Specific examples of components and arrangements aredescribed below to simplify the present disclosure. These are, ofcourse, merely examples and are not intended to be limiting. Moreover,the formation of a first feature over or on a second feature in thedescription that follows may include embodiments in which the featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed interposing the features, such thatthe features may not be in direct contact. Various features may bearbitrarily drawn in different scales for the sake of simplicity andclarity.

Illustrated in FIG. 1 is a flowchart of a method 20 for fabricating asemiconductor device according to various aspects of the presentdisclosure. Referring to FIG. 1, the method 20 begins with block 22, inwhich a silicon substrate having opposite first and second sides isprovided. The method continues with block 24, in which a highcoefficient-of-thermal-expansion (CTE) layer is formed on the first sideof the silicon substrate. The high CTE layer has a CTE greater than theCTE of silicon. The method 20 continues with block 26, in which a bufferlayer is formed over the second side of the silicon substrate. Thebuffer layer has a CTE greater than the CTE of silicon. The method 20continues with block 28, in which a III-V family layer is formed overthe buffer layer. The III-V family layer has a CTE that is greater thanthe CTE of the buffer layer.

FIGS. 2 to 6 are diagrammatic fragmentary cross-sectional side views ofa semiconductor device at various fabrication stages according toembodiments of the method 20 of FIG. 1. It is understood that FIGS. 2 to6 have been simplified for a better understanding of the inventiveconcepts of the present disclosure.

Referring to FIG. 2, a silicon wafer 40 is provided. The silicon wafer40 may also be referred to as a silicon substrate 40. The silicon wafer40 has a thickness 45. In an embodiment, the thickness 45 is in a rangefrom about 500 microns (um) to about 1000 um. The silicon wafer 40 alsohas a side or a surface 50, and a side or a surface 60 that is locatedopposite the side 50. Since the side 50 is located above the side 60 inFIG. 2, the side 50 may also be referred to as a front side, and theside 60 may also be referred to as a backside.

The side 50 and side 60 each have a silicon (111) surface. The silicon(111) surface is obtained by cleaving or cutting the silicon along a(111) lattice plane defined according to a Miller Index. In anembodiment, the silicon wafer 40 has a lattice constant that is in arange from about 3.8 angstroms to about 3.9 angstroms, and acoefficient-of-thermal-expansion (CTE) that is in a range from about2.5×10⁻⁶/° C. to about 2.7×10⁻⁶/° C. It is understood that all thelattice constants discussed in this disclosure are measured at about 300degrees Kelvin.

The silicon wafer 40 is chosen to have the silicon (111) surface becauseit has a relatively small mismatch with a buffer layer (containing agallium nitride material or an aluminum gallium nitride material), whichwill be formed on the silicon (111) surface in the following process.Had a different silicon surface been used, such as a silicon (100)surface, the mismatch between the silicon (100) surface and the bufferlayer would have been greater and consequently would have led to morefabrication difficulties.

A buffer layer 70 is formed on the side 50 of the silicon wafer 40. Thebuffer layer 70 has a thickness 75. In an embodiment, the thickness 75is in a range from about 1 um to about 2 um. The buffer layer 70 may beformed by a metal-organic chemical vapor deposition (MOCVD) process. Inan embodiment, the MOCVD process is performed at a temperature in arange from about 800 degrees Celsius to about 1400 degrees Celsius, andfor a process duration time in a range from about 1 hour to about 3hours.

The buffer layer 70 may include a plurality of thin layers of aluminumnitride or aluminum gallium nitride. These thin layers of aluminumnitride or aluminum gallium nitride may each be as thin as a fewnanometers (nm) or tens of nanometers. An aluminum nitride material mayhave a lattice constant that is in a range from about 2.9 to about 3.3and a CTE that is in a range from about 3.8×10⁻⁶° C. to about 4.5×10⁻⁶/°C. The lattice constant and the CTE of an aluminum gallium nitridematerial are close to those of the aluminum nitride. Therefore, thebuffer layer 70 and the silicon wafer 40 have mismatched CTEs.

In one embodiment, the buffer layer 70 is implemented as a lowtemperature aluminum nitride structure, in which a plurality of aluminumnitride layers as thin as a few nanometers are interleaved with aplurality of gallium nitride layers as thin as a few hundred nanometers.In another embodiment, the buffer layer 70 is implemented as asuper-lattice structure, in which a gallium nitride/aluminum nitridesuper-lattice is formed at high temperatures, for example temperaturesas high as about 1050 degrees Celsius. In yet another embodiment, thebuffer layer is implemented as a step graded aluminum gallium nitridestructure. In an embodiment, the step graded aluminum gallium nitridestructure includes aluminum nitride layers, a graded aluminum galliumnitride layer, and a fixed aluminum gallium nitride layer. These layersmay be formed at different temperatures. It is understood that thebuffer layer 70 is not limited to the structures discussed above, andmay be implemented differently in other embodiments.

After the buffer layer 70 is formed, the silicon wafer 40 and the bufferlayer 70 are cooled down to about a room temperature, which is in arange from about 20 degrees Celsius to about 30 degrees Celsius in anembodiment. During the cooling, the CTE mismatch between the bufferlayer 70 and the silicon wafer 40 means that the buffer layer 70 and thesilicon wafer contract at different rates. In more detail, since the CTEof the buffer layer 70 is greater than the CTE of the silicon wafer, atensile stress is generated. In general, stress is a measure of internalforces acting within a deformable body. A tensile stress involves aforce acting outward from the plane, whereas a compressive stressinvolves a force acting inward to a plane. Here, the tensile stresspulls the edges of the silicon wafer 40 upwards, resulting in a slightlyconcave shape. It may be said that the wafer 40 is slightly distorted,which is also referred to as wafer bow. For the sake of simplicity, thewafer distortion is not shown in FIG. 2.

Referring now to FIG. 3, high CTE layers 80 and 90 are formed on thebuffer 70 and the side 60 of the silicon wafer, respectively. The highCTE layers 80 and 90 each have a CTE that is greater than about 3×10⁻⁶1°C. In an embodiment, the high CTE layers 80 and 90 each include asilicon nitride material. The silicon nitride material has a CTE that isin a range from about 3×10⁻⁶/° C. to about 3.4×10⁻⁶1° C., which ishigher than that of silicon.

The high CTE layers 80 and 90 are formed using a low-pressure chemicalvapor deposition (LPCVD) process. In an embodiment, the LPCVD process isperformed at a temperature in a range from about 500 degrees Celsius toabout 900 degrees Celsius, and for a process duration time in a rangefrom about 3 hours to about 10 hours.

The high CTE layer 90 has a thickness 95. In an embodiment, thethickness 95 is less than about 2 um, for example in a range from about0.5 um to about 2.0 um. The thickness 95 is not randomly chosen, but israther calculated by a set of equations (to be discussed later). Thethickness 95 is calculated to have an optimized value, such that thehigh CTE layer 90 can generate a compressive stress to counteract orbalance against a tensile stress generated by the buffer layer 70 and agallium nitride layer to be formed later. The calculation of thethickness 95 will be discussed in more detail later.

After the high CTE layers 80 and 90 are formed, the overall device iscooled to room temperature again. The CTE mismatches during the coolingwill once again result in an approximately concave shape for the overalldevice. For the sake of simplicity, the concave shape is not illustratedin FIG. 3.

Referring now to FIG. 4, the high CTE layer 80 above the buffer layer 70is removed. The removal may be carried out using a wet etching processknown in the art, or another suitable process. The removal of the highCTE layer 80 will cause the stresses to shift within the overall device,such that the overall device—including the silicon wafer 40, the bufferlayer 70, and the high CTE layer 90—to bend downwards from the edges. Inother words, the edges of the overall device are pulled down by the highCTE layer 90 and will now have a convex shape. Once again, for reasonsof simplicity, the convex shape is not specifically illustrated in FIG.4.

Referring now to FIG. 5, a gallium nitride layer 100 is formed over thebuffer layer 70. The gallium nitride layer 100 may also be referred toas a III-V family or a III-V structure, because gallium is in the “III”family of the periodic table, and nitrogen is in the “V” family of theperiodic table. A gallium nitride material may have a lattice constantthat is in a range from about 3 to about 3.4 and a CTE that is in arange from about 5.1×10⁻⁶/° C. to about 6.1×10⁻⁶/° C. The galliumnitride layer 100 has a slightly higher lattice constant and a slightlyhigher CTE than the buffer layer 70.

In an embodiment, the gallium nitride layer 100 is formed by a MOCVDprocess. In an embodiment, the MOCVD process is performed at atemperature in a range from about 800 degrees Celsius to about 1400degrees Celsius, and for a process duration time in a range from about 1hour to about 3 hours. The gallium nitride layer 100 has a thickness105. In an embodiment, the thickness 105 is in a range from about 1 umto about 4 um.

As discussed above, the silicon wafer 40 is chosen to have the silicon(111) surface so that its lattice constant is better matched with thatof the buffer layer 70. By using the silicon wafer with the silicon(111) surface, and by adjusting the implementation scheme of the bufferlayer 70, different lattice constant mismatches may be achieved at thevarious layer interfaces, which causes different stresses. Here, thelattice constant mismatches may be adjusted in a manner such that theentire device—including the silicon wafer 40 and the layers 70, 90 and100—has a slightly convex shape at the high temperature range (fromabout 800 degrees Celsius to about 1400 degrees Celsius).

Thereafter, the overall device is cooled down to room temperature.According to an embodiment of the disclosure, the MOCVD processes usedto form the buffer layer 70 and the gallium nitride layer 100 and theLPCVD process used to form the high CTE layers 80 and 90 are performedusing different tools. Therefore, the silicon wafer 40 and the layersformed thereon have to be cooled after the formation of the buffer layer70, after the formation of the high CTE layers 80 and 90, and after theformation of the gallium nitride layer 100.

As the overall device is cooled, the various layers contract accordingto their respective CTEs. A layer with a greater CTE contracts more thana layer with a lower CTE. The different rates of contraction will causestress between adjacent layers. The amount of stress is also dependenton the thickness of the layers. For example, as a layer becomes thicker,its contribution to the amount of stress will increase accordingly.

Here, since the material composition of the buffer layer 70 is similarto that of the gallium nitride layer 100, and their CTEs are not toodifferent, the buffer layer 70 and the gallium nitride layer 100 mayroughly be viewed as a collective entity in performing stresscalculations as well.

The high CTE layer 90 has a higher CTE than the silicon wafer 40. Ascooling occurs, the buffer layer 70/gallium nitride layer 100 contractmore than the silicon wafer 40, which creates tensile stress at theinterface between the silicon wafer 40 and the buffer layer 70/galliumnitride layer 100. Meanwhile, the high CTE layer 90 contracts more thanthe silicon wafer 40 due to the higher CTE of the high CTE layer 90.This creates compressive stress that counteract against the tensilestress created by the contraction of the buffer layer 70/gallium nitridelayer 100. Stated differently, the high CTE layer 90 and the bufferlayer 70/gallium nitride layer 100 are pulling the silicon wafer 40 inopposite directions, which has a balancing effect. Without the high CTElayer 90, the overall device would have been pulled by the buffer layer70/gallium nitride layer 100 to have a concave shape. Here, the high CTElayer 90 acts to reduce the pulling by the buffer layer 70/galliumnitride layer 100, and the final shape of the overall device issubstantially flat.

In an embodiment, the thickness 95 of the high CTE layer 90 iscalculated so that the stress created by the high CTE layer 90 willsubstantially balance against the stress created by the buffer layer70/gallium nitride layer 100, as the overall device is cooled to theroom temperature range. Even if the balancing does not occur perfectly,the remaining amount of stress can be easily absorbed by the siliconwafer 40 without causing damage, because the silicon wafer 40 is so muchthicker than all the other layers. In this manner, the high CTE layer 90helps reduce distortion to the overall device by generating stress to atleast partially cancel out the stress generated by the buffer layer70/gallium nitride layer 100. Had the high CTE layer 90 not beeninserted, the stress due to the buffer layer 70/gallium nitride layer100 would have distorted or warped the shape of the overall device,including the silicon wafer 40 and the gallium nitride layer 100. Butsince the high CTE layer 90 counteracts against the buffer layer70/gallium nitride layer 100 during the cooling, the overall device willachieve a substantially flat shape after the cooling. For example, atthe end of the cooling, the overall device may achieve a waferdistortion or wafer bow of less than 25 um.

The following equations provide more mathematical details to the stresscalculations discussed above:

σ(E_(i)^(′), R_(i), d_(i)) = σ₁ + σ₂ + σ₃$\sigma_{1} = {{{- \frac{E_{1}^{\prime}d_{1}^{2}}{6}}\left( {\frac{1}{R_{2}} - \frac{1}{R_{1}}} \right)} + \frac{E_{1}^{\prime}Y_{1}}{R_{2}}}$$\sigma_{2} = {{- \frac{E_{1}^{\prime}d_{1}^{2}}{6d_{2}}}\left( {\frac{1}{R_{2}} - \frac{1}{R_{1}}} \right)}$$\sigma_{3} = {\frac{E_{1}^{\prime}d_{1}^{2}}{6d_{3}}\left( {\frac{1}{R_{3}} - \frac{1}{R_{2}}} \right)}$$E_{i}^{\prime} = \frac{E_{i}}{1 - v_{i}}$

where a is the stress of a layer, d is the thickness of a layer, E isthe stress coefficient of a layer, R is the curvature of a layer, and vis the poisson's ratio of a layer. The subscripts 1, 2, and 3 refer thesilicon wafer 40, the high CTE layer 90, and the combination of thebuffer layer 70 and the gallium nitride layer 100 collectively.

Based on the above set of equations, the thickness 95 (appearing as d₂in the equations) of the high CTE layer 90 can be calculated so that theoverall device has a distortion that is less than about 25 um. Forexample, the sum of the stresses (σ₁, σ₂, and σ₃) may be set to 0, andd₂ can be calculated accordingly by manipulating the above equations. Inone embodiment, d₂ (or the thickness 95) is calculated to be less thanabout 2 um, for example within a range from about 1 um to about 2 um.

From the discussions above, it can be seen that the present disclosureoffers a method to form a gallium nitride material on a silicon wafer,without causing distortion to the wafer. This method can be applied indifferent fields of semiconductor technologies that may involve galliumnitride growth on a substrate. For example, it can be used to fabricatehigh power semiconductor devices, an example of which is shown in FIG.6.

Referring to FIG. 6, a diagrammatic fragmentary cross-sectional sideview of a high power semiconductor device 120 is illustrated. Thesemiconductor device 120 includes the silicon wafer 40, which is used inpart to provide mechanical support for the layers formed thereon. Thesemiconductor device 120 includes the high CTE layer 90 for stressbalancing purposes. The semiconductor device 120 also includes thesilicon wafer 40, the buffer layer 70, and the gallium nitride layer100. The gallium nitride layer 100 has the thickness 105. In anembodiment, the thickness 105 is in a range from about 1 um to about 4um.

The high power semiconductor device 120 also includes an aluminumgallium nitride layer 140 that is formed over the gallium nitride layer100. The aluminum gallium nitride layer 140 has a chemical formulaAl_(x)Ga_(1-x)N, where x is in a range from about 0.25 to 0.3. Thealuminum gallium nitride layer 140 has a thickness 150. In anembodiment, the thickness 150 is in a range from about 10 nm to about 40nm.

The high power semiconductor device 120 also includes a transistorformed by a gate device 160 and source/drain regions 170. The gatedevice 160 (or gate structure) is formed over the aluminum galliumnitride layer 140, and source/drain regions 170 are formed in thealuminum gallium nitride layer 140 and partially in the gallium nitridelayer 100. The gate device 160 may include a gate dielectric componentand a gate electrode component. The source/drain regions 170 may beformed by one or more doping or implantation processes. When thetransistor device is turned on, a conductive channel is formed below thegate device 160 and between the source/drain regions 170. An electricalcurrent will flow in the conductive channel.

The high power semiconductor device 120 also includes an interconnectstructure 200 formed over the aluminum gallium nitride layer 140. Theinterconnect structure 200 includes a plurality of interconnect layers,also referred to as metal layers. Each metal layer contains a pluralityof metal lines that route electrical signals. The metal layers areinterconnected together by vias. Contacts are also formed over the gatedevice 160 and the source/drain regions 170 so that connections may beestablished with external devices. For the sake of simplicity, thesemetal lines, vias and contacts are not specifically illustrated in FIG.7. Also, additional fabrication processes may be performed to finish thefabrication of the high power device 120, such as passivation, testing,and packaging processes. These processes are also not shown or discussedherein for reasons of simplicity.

It is understood that the high power device 120 illustrated in FIG. 7and discussed above are provided merely to provide an example of how thehigh CTE layer 90 may be used to facilitate forming a gallium nitridelayer on a silicon wafer. In other embodiments, the high CTE layer 90may be used to form light-emitting diode (LED) devices, radio-frequency(RF) devices, and high electron mobility transistor (HEMT) devices. Infact, as long as it is desirable to form a III-V family layer on asilicon substrate without substantial distortion, the method andstructure disclosed by the present disclosure may be applied.

FIGS. 7-9 are diagrammatic fragmentary cross-sectional side views of asemiconductor device at different stages of fabrication according toanother embodiment of the present disclosure. For the sake ofconsistency and clarity, similar elements are labeled the same in FIGS.2-6 and 7-9.

Referring to FIG. 7, a glass layer 220 is bonded to the side 60 of thewafer 40. The glass layer 220 has a CTE that is in a range from about3.0×10⁻⁶/° C. to about 5.5×10⁻⁶/° C. The glass layer 220 has a meltingtemperature in a range from about 1400 degrees Celsius to about 1800degrees Celsius. In an embodiment, the glass layer 220 is doped toincrease its CTE. The glass layer 220 has a thickness 230. In anembodiment, the thickness 230 is in a range from about 500 um to about1500 um.

Referring now to FIG. 8, the glass layer 220 is thinned from the side 60in a thinning process 240. The thinning process 240 substantiallyreduces the thickness of the glass layer 220 down to a thickness 250. Inan embodiment, the thickness 250 is less than about 2 um, for example ina range from about 1 um to about 2 um. In an other embodiment, the sumof the thicknesses 45 and 250 is about the same as a thickness ofanother silicon wafer that could have been used instead of the siliconwafer 40, where the other silicon wafer would have had a silicon (100)surface as opposed to the silicon (111) surface of the silicon wafer 40.However, as discussed before, the use of the silicon (100) surfaceresults in a greater lattice constant mismatch between the silicon waferand the gallium nitride layer formed thereon, and as such isundesirable. Thus, the embodiment discussed herein does not use thesilicon wafer with the (100) surface.

Referring now to FIG. 9, the buffer layer 70 is formed over the side 50of the silicon wafer 40, and the gallium nitride layer 100 is formedover the buffer layer 70. The buffer layer 70 and the gallium nitridelayer 100 may be formed using the same processing tools and at the sametemperature range. Thereafter, the aluminum gallium nitride layer 140 isformed over the gallium nitride layer 100, the gate device 160 and thesource/drain regions 170 are formed, and the interconnect structure 200is also formed in a similar manner as those described above withreference to FIG. 6. Here, the thinned glass layer 220 serves as thehigh CTE layer and helps reduce distortion of the overall device as itis cooled.

FIGS. 10-11 are diagrammatic fragmentary cross-sectional side views of asemiconductor device at different stages of fabrication according to yetanother embodiment of the present disclosure. For the sake ofconsistency and clarity, similar elements are labeled the same in FIGS.2-6 and 10-11.

Referring to FIG. 10, a silicon carbide layer 270 formed on the side 60of the wafer 40. The silicon carbide layer 270 has a CTE that is in arange from about 4.3×10⁻⁶° C. to about 4.7×10⁻⁶/° C. The silicon carbidelayer 270 has a thickness 280. In an embodiment, the thickness 280 is ina range from about 500 um to about 1500 um.

Referring now to FIG. 11, the buffer layer 70, the gallium nitride layer100, the aluminum gallium nitride layer 140, the gate device 160, thesource/drain regions 170, and the interconnect structure 200 are allformed in a manner similar to those described above with reference toFIG. 6. Here, the silicon carbide layer 270 serves as the high CTE layerand helps reduce distortion of the overall device.

The embodiments of the present disclosure discussed above offeradvantages over existing methods. It is understood, however, that otherembodiments may offer different advantages, and that no particularadvantage is required for any embodiment. One of the advantages is thatthe overall device will remain substantially flat during fabrication,which helps reduce wafer defects. In traditional fabrication processes,the wafer may become distorted at one stage or another. Wafer distortionis undesirable because it may lead to wafer defects, thus reducing yieldand/or degrading device performing and quality.

In comparison, the embodiments discussed above utilize the high CTElayer 90 (or other similar high CTE layers) to help reduce waferdistortion during fabrication. When the overall device is cooled to aroom temperature from the high temperature used to form the galliumnitride layer 100, the high CTE layer 90 helps counteract stressescreated as a result of different CTEs and different contraction rates.The thickness 95 of the high CTE layer 90 may be calculated andimplemented so that the stresses are still balanced as the overalldevice is cooled. Hence, the overall device is substantially flat afterthe cooling process, and therefore defects related to wafer distortionmay be reduced.

Another advantage is that the high CTE layer 90 is inexpensive to form,and its fabrication is compatible with existing fabrication processflow. Therefore, the insertion of the high CTE layer between the siliconwafer and the gallium nitride layer has minimal impact on fabricationcosts.

One of the broader forms of the present disclosure involves a method.The method includes providing a silicon wafer having opposite first andsecond sides. The method includes forming a layer over the first side ofthe silicon wafer. The layer has a coefficient-of-thermal-expansion(CTE) that is higher than that of silicon. The method includes forming aIII-V family layer over the second side of the silicon wafer. The III-Vfamily layer has a CTE that is higher than that of silicon.

Another of the broader forms of the present disclosure involves a methodof fabricating a semiconductor device. The method includes providing asilicon substrate having opposite first and second sides. At least oneof the first and second sides includes a silicon (111) surface. Themethod includes forming a high coefficient-of-thermal-expansion (CTE)layer on the first side of the silicon substrate. The high CTE layer hasa CTE greater than the CTE of silicon. The method includes forming abuffer layer over the second side of the silicon substrate. The bufferlayer has a CTE greater than the CTE of silicon. The method includesforming a III-V family layer over the buffer layer. The III-V familylayer has a CTE greater than the CTE of the buffer layer.

Still another of the broader forms of the present disclosure involves asemiconductor device. The semiconductor device includes a siliconsubstrate having opposite first and second sides. The silicon substratehas a first coefficient-of-thermal-expansion (CTE). The semiconductordevice includes a high CTE layer disposed over the first side of thesilicon substrate. The high CTE layer has a third CTE that is greaterthan the first CTE. The semiconductor device includes a III-V familylayer disposed over the second side of the silicon substrate. The III-Vfamily layer has a second CTE that is greater than the first CTE.

The foregoing has outlined features of several embodiments so that thoseskilled in the art may better understand the detailed description thatfollows. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A method of fabricating a semiconductor device,comprising: providing a silicon substrate having opposite first andsecond sides, at least one of the first and second sides including asilicon (111) surface; forming a first highcoefficient-of-thermal-expansion (CTE) layer on the first side of thesilicon substrate, the first high CTE layer having a CTE greater than aCTE of silicon; forming a buffer layer over the second side of thesilicon substrate, the buffer layer having a CTE greater than the CTE ofsilicon; forming a second high CTE layer over the second side of thesilicon substrate, the second high CTE layer having a CTE greater thanthe CTE of silicon; removing the second high CTE layer; and afterremoving the second high CTE layer, forming a III-V family layer overthe buffer layer, the III-V family layer having a CTE greater than theCTE of the buffer layer.
 2. The method of claim 1, wherein: the formingthe high CTE layer is carried out in a manner so that the first high CTElayer includes a material selected from the group consisting of: siliconnitride, doped glass, and silicon carbide; and the forming the III-Vfamily layer is carried out in a manner so that the III-V family layerincludes a gallium nitride material.
 3. The method of claim 1, whereinthe forming the first high CTE layer is carried out in a manner so thatthe first high CTE layer has a thickness that is in a range from about0.5 microns to about 2 microns.
 4. The method of claim 1, wherein theforming the first high CTE layer is carried out in a manner so that theCTE of the first high CTE layer is greater than about 3×10⁻⁶/° C.
 5. Themethod of claim 1, wherein the forming the buffer layer is carried outin a manner so that the buffer layer includes a plurality of layers ofaluminum nitride material and the CTE of the buffer layer is in a rangefrom about 3.8×10⁻⁶/° C. to about 4.5×10⁻⁶/° C.
 6. The method of claim1, wherein the forming the III-V family layer is carried out using anepitaxial growth process, the epitaxial growth process being performedat a temperature range from about 800 degrees Celsius to about 1400degrees Celsius; and after the epitaxial growth process is performed,cooling the III-V family layer and the silicon substrate to about a roomtemperature.
 7. The method of claim 1, further comprising forming asource/drain feature in the III-V family layer.
 8. A method comprising:forming a first material layer having a firstcoefficient-of-thermal-expansion (CTE) on a first side of a substrate;forming a second material layer having a second CTE on a second side ofthe substrate that is opposite the first side, the second CTE beingdifferent than the first CTE; forming a third material layer over thefirst material layer on the first side of the substrate, the thirdmaterial layer having a third CTE that is different than the first CTE;removing the third material layer over the first material layer; forminga III-V family material layer over the first material layer on the firstside of the substrate; and forming a source/drain feature in the III-Vfamily material layer.
 9. The method of claim 8, further comprisingforming another III-V family material layer over the third materiallayer prior to forming the III-V family material layer over the firstmaterial layer.
 10. The method of claim 9, wherein forming thesource/drain feature in the III-V family material layer further includesforming the source/drain feature in the another III-V family materiallayer.
 11. The method of claim 9, wherein the III-V family materiallayer includes gallium aluminum nitride, and wherein the another III-Vfamily material layer includes gallium nitride.
 12. The method of claim8, wherein the second CTE is less than the first CTE, and wherein thethird CTE is the same as the second CTE.
 13. The method of claim 8,wherein the substrate includes silicon and the first surface has a (111)orientation.
 14. The method of claim 8, wherein removing the thirdmaterial layer over the first material layer occurs prior to forming thesource/drain feature in the III-V family material layer.
 15. A methodcomprising: forming a first material layer having a firstcoefficient-of-thermal-expansion (CTE) on a first side of a substrate,wherein the substrate has a second CTE that is different than the firstCTE; forming a second material layer having a third CTE on a second sideof the substrate that is opposite the first side, the third CTE beingdifferent than the second CTE; forming a third material layer over thefirst material layer on the first side of the substrate, wherein thethird material layer has a fourth CTE that is different than the secondCTE; forming a III-V family material layer over the first material layeron the first side of the substrate, wherein the III-V material layer isdifferent from the third material layer; and forming a source/drainfeature in the second III-V family material layer that extends beyondthe III-V family material layer towards the substrate.
 16. The method ofclaim 15, removing the third material layer over the first materiallayer prior to forming the III-V family material layer.
 17. The methodof claim 15, reducing a thickness of the second material layer prior toforming the first material layer having the first CTE on the first sideof the substrate.
 18. The method of claim 15, wherein the secondmaterial layer includes at least one of glass and silicon carbide. 19.The method of claim 15, further comprising forming a gate structuredirectly on the III-V family material layer such that the gate structurephysically contacts the III-V family material layer.
 20. The method ofclaim 15, wherein the third material layer includes a III-V familymaterial and the source/drain feature extends into the third materiallayer.